(1) Field of the Invention
The present invention relates generally to semiconductor storage cells, and more particularly, to dynamic analog or multilevel RAM (DRAM) cells using a natural transistor.
(2) Description of the Prior Art
Dynamic RAM (DRAM) is a type of RAM that only holds its data if it is continuously accessed by a special logic called a refresh circuit. Many hundreds of times each second, this circuitry reads and then re-writes the contents of each memory cell, whether the memory cell is being used at that time by a processor or not. If this is not done, then the DRAM will lose its content, even if it continues to have power supplied to it. This refreshing action is why the memory is called dynamic.
Dynamic memory cells store a data bit in a small capacitor. The advantage of this type of cell is that it is very simple, thus allowing very large memory arrays to be constructed on a chip at low cost. FIG. 1 prior art shows principally a dynamic RAM (DRAM) cell capable of storing a single bit of information. Said memory cell is consisting of a single MOS transistor 1 and a capacitor 2.
In this type of cell, the transistor acts as a switch, allowing the capacitor to be charged or discharged or, in other words, to store a “1” or a “0”.
A challenge to the designers of DRAM cells is power consumption and the ability to store not just two levels (“0” or “1”) but also more levels of information in one DRAM cell.
There are various patents available dealing with said problems:
U.S. Pat. No. 6,373,767 to Patti describes a multi-level memory in which each storage cell stores multiple bits. The memory includes a plurality of storage words, a data line, a plurality of reference lines, and a read circuit. Each storage word includes a data memory cell and a plurality of reference memory cells. A stored charge determines a conductivity value measurable between the first and second terminals of each memory cell. The read circuit generates a digital value indicative of the value stored in the data memory cell of a storage word that is connected to the data and reference lines by comparing the conductivity of the data line with a continuous conductivity curve determined by the conductivities of the reference lines.
U.S. Pat. No. 6,282,115 to Furukawa et al. discloses a multi-level memory cell capable of storing two or three bits of digital data occupying only four lithographic squares and requiring only one or two logic level voltage sources, respectively. High noise immunity derives from integration of the multi-level signal in the memory cell directly from logic level digital signals applied to two capacitors (as well as the bit line for the eight level mode of operation) by using capacitors having different values in order to avoid digital-to-analog conversion during writing. The capacitors can be simultaneously written and read to reduce memory cycle time. Transistor channels and capacitor connections are formed on adjacent semiconductor pillars using plugs of semiconductor material between pillars as common gate structures and connections. Opposite surfaces of the pillars also serve as storage nodes with common capacitor plates formed by conformal deposition between rows of plugs and pillars.
U.S. Pat. No. 4,335,450 to Thomas describes a non-destructive read out memory cell system having a semiconductor substrate supporting an array of memory cells each of which includes a field effect transistor having a source and a drain defining a channel region having high and low threshold sections. In a first embodiment the channel region is further defined by the upper surface of the semiconductor substrate, and in second and third embodiments the channel region is further defined by a V-groove and by a U-groove, respectively, formed in the substrate. A gate electrode separated from the surface of the semiconductor substrate by a thin insulating layer is disposed over the channel region. A storage node, preferably an N+ diffusion region, is located within the substrate adjacent to the high threshold section of the channel region. Pulsing means are provided for selectively charging and discharging the storage node and sensing means are provided to determine the flow of current passing through the channel region, which is representative of the binary information contained on the storage node. Since the memory cells of the system of the present invention are current sensitive and since these cells hold charge for a relatively long period of time compared with conventional dynamic device memory cells, the system may be used for multilevel storage.